1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly, to integrated circuit memory devices fabricated using standard processing techniques used to fabricate core circuitry transistor devices.
2. Description of the Related Art
In the design of integrated circuit devices, there is often a need to integrate some sort of non-volatile memory storage elements among other logic processing transistors. In today's integrated circuit implementations, non-volatile memory storage elements are being used to achieve functional customization (e.g., as in FPGAs), or store codes for tracking purposes and store security/authorization codes to prevent pirating of information or services. However, the integration of only a few storage elements in selected application specific integrated circuits (ASICs) incurs the additional cost of complicating the semiconductor processing operations implemented to make the ASIC. For example, when a non-volatile memory storage element is fabricated along with standard transistors that are implemented in the ASIC design, many more processing operations will be required in order to fabricate special high voltage transistors and tunneling transistors that that are needed to make the non-volatile memory storage devices. As will be described below, the additional fabrication is needed because the junctions and gate oxides of normal ASCI transistors are not able to withstand the high voltages needed to program the memory cells.
Traditionally, non-volatile memory storage elements are arranged as arrays of cells that can be written to and read from by accessing selected rows and columns. FIG. 1A shows an example of a non-volatile storage memory 100 (and access circuitry), including a memory array 102 having a plurality of rows and columns. For simplicity, the intersection of a row 112 and a column 114 will define the location of a selected cell 116. The memory access circuitry typically includes a row select unit 104 that enables access to a specific row 112 of the memory array 102, and a column select unit 106 that enables selective access to a particular column 114 of the memory array 102.
In typical designs, a Vpp programming voltage pump generator 108 is provided in electrical communication with the row select 104 and the column select 106. The Vpp pump generator 108 is configured to provide a high voltage typically in the range of about 12-14 volts to both the row select 104 and the column select 106 during a programming operation. The row select unit 104 typically includes a number of high voltage transistors which enable the generation and steering of a high voltage onto the selected row, which is greater than Vpp by a voltage threshold Vtn, for an N-type transistor (i.e., Vpp+Vtn). Accordingly, the voltage output onto row 112 by the row select unit 104 will typically be about 13-15 volts, which is a volt higher than the Vpp voltage generated by the Vpp pump generator 108. The column select 106 on the other hand, will generally include a latching circuit which outputs a voltage equal to Vpp onto the selected column 114 when the appropriate column address is provided to a gate 110, or other well known circuitry. Also shown is a gate 111 that is connected to the column select 106.
FIG. 1B shows an exemplary storage cell 116 which is defined at an intersection of the row 112 and the column 114 of the memory array 102. In this example, the storage cell 116 includes a pass gate transistor 126, which has one terminal connected to the column 114 and its other terminal connected to the drain and source of a transistor 120. The transistor 120 forms a Fowler/Nordheim tunneling diode, and has a common gate 120a that is coupled to gates of transistor 122 and 124. The special structure of the transistor 120 will be described in greater detail below with reference to FIG. 1D. Transistor 122 is configured to create the necessary electric field to get the appropriate charge onto or off of the storage cell 116, and transistor 124 is generally a sense transistor which enables the determination of whether a logical one or a logical zero is stored in the storage cell 116.
Turning now to FIG. 1C, a semiconductor cross section 130 is shown illustrating a high voltage transistor which is used to steer the necessary high voltage to the storage cell 116. In conventional row select 104 and column select 106 circuitry, such high voltage transistors are needed to withstand the high voltages provided by the Vpp pump generator 108 and to steer them to the storage cell 116. Accordingly, the semiconductor processing operations performed in order to make the high voltage steering transistor will typically include processing operations which are not the same as those needed to make transistors for core ASIC circuitry.
In this example, the high voltage steering transistor is fabricated over a P-type substrate 132. The structure typically includes conventional field oxide 131 to isolate the transistor from others on the semiconductor substrate. Initially, the source and drain regions 134 are doped with a phosphorous (Ph) dopant such that a very deep junction is created. These deep junctions are typically roughly twice the depth of those used for standard low voltage ASIC processing The deeper source and drain junction regions 134 are need in order to raise the junction breakdown level. In addition, high voltage steering transistors will also have a longer channel in order to increase the grounded gate breakdown.
The high voltage steering transistors also require specialized fabrication in order to form thicker gate oxides 138, which are in the range of about 150 angstroms or greater, which are configured to withstand voltages that are as high as 15 volts. This greater thickness of 150 angstroms should be compared to the typical gate oxide thicknesses of about 65 angstroms used in a standard 0.25 micron process within the core of an ASIC. However, because the gate oxide is fabricated to such increased thicknesses, an additional impurity implantation 136 needs to be made in the channel region between the source and drain regions 134. This special implant is usually a boron dopant, which is configured to adjust the voltage threshold of the high voltage steering transistor to compensate for the thicker oxide 138. Also shown is a polysilicon gate 140 which is defined over the thicker oxide 138.
At this point, it should be appreciated that the fabrication of high voltage steering transistors will require the formation of deeper drain source regions 134, an added step to implant the dopant 136 between the drain and source regions 134, and a thicker oxide 138. All of these special fabrication steps are different and in addition to those performed in fabricating standard 0.25 micron transistor devices, and therefore add significantly to the complexity of fabricating memory devices on the same chip along with custom ASIC transistor devices. In addition, the transistors of the ASCI design must be subjected to all of the additional fabrication steps, even when only a relatively small number of memory cells are needed.
FIG. 1D shows a cross sectional view of transistor 120 of FIG. 1B. Transistor 120 also requires special fabrication steps which are different than those performed in making conventional low voltage transistor devices. For example, transistor 120 will generally require the fabrication of source drain regions 142 and a special implant 142a, which connects the source and drain regions 142. For example, if the source and drain regions 142 are N-type regions, the special implant 142a will also be an N-type dopant region. The formation of the special N-type implant region 142a will keep the channel of the storage transistor 120 from turning off when the gate voltage is negative with respect to the drain/source.
The transistor 120 also needs a specially fabricated gate oxide 144, having a thin tunnel oxide region 144a. As is well known, in order to fabricate the thin tunnel oxide region 144a, that portion of the gate oxide needs to be masked off midway through the growth of the oxide 144, and then the masking material must be removed after the gate oxide 144 has been grown to its desired thickness. By using these extra masking steps, the thinner tunnel oxide region 144 can be formed. Once the thinner tunnel oxide region 144a has been formed, a polysilicon gate 120a is formed over the tunnel oxide region 144a. As was the case with the high voltage steering transistor 130, the special transistor 120 also requires processing operations which are different than those required for traditional low voltage transistor devices, which are commonly designed throughout an ASIC design. As a recap, the fabrication of transistor 120 requires a special implant 142a, and a specially fabricated thin tunnel oxide region 144a.
Each of these special fabrication operations needed to make the transistor 120 and the high voltage steering transistors necessarily add to the number of processing operations required to fabricate the transistors in the core of an ASIC device. As is well known, ASIC devices typically have hundreds of thousands or even millions of transistor devices that are fabricated with standard transistor structures. Therefore, if only one non-volatile storage device is fabricated on the same chip along with the ASIC device transistors, the processing complexities of making an ASIC device will unfortunately multiply significantly due to the special fabrication needed to make the memory element devices.
In view of the foregoing, there is a need for a non-volatile memory storage cell that can be fabricated along with core ASIC circuitry without further complicating the process fabrication of standard transistor devices.